-1
Привет, я все еще новичок в письменном виде в системном verilog. Сегодня я столкнулся с этими ошибками. Я знаю, что это значит, но я не мог понять, где ошибка. Было бы неплохо, если бы кто-то здесь мог помочь мне указать, где он находится.10028 10166 и 10029 Ошибка Quartus
module control
(
/* Input and output port declarations */
input clk,
/* Datapath controls */
/* Datapath to control */
input lc3b_opcode opcode,
input br_en,
input bit4,
input bit5,
input bit11,
input logic mem_byte,
/* Control to datapath */
output logic load_pc,
output logic load_ir,
output logic load_regfile,
output logic load_mar,
output logic load_mdr,
output logic load_cc,
output logic [1:0] pcmux_sel,
output logic storemux_sel,
output logic [1:0] alumux_sel,
output logic [2:0] regfilemux_sel,
output logic [1:0] marmux_sel,
output logic mdrmux_sel,
output logic [1:0] addr1mux_sel,
output logic hilomux_sel,
output lc3b_aluop aluop,
/* Memory signals */
input mem_resp,
output logic mem_read,
output logic mem_write,
output lc3b_mem_wmask mem_byte_enable
);
enum int unsigned {
/* List of states */
fetch1,
fetch2,
fetch3,
decode,
s_add,
s_and,
s_not,
s_jmp,
s_lea,
s_trap,
s_ldb,
s_ldi,
s_sti,
s_stb,
s_jsr,
trap1,
trap2,
br,
br_taken,
calc_addr,
ldr1,
ldr2,
ldb1,
ldb2,
ldi1,
ldi2,
ldi3,
sti1,
sti2,
sti3,
stb1,
stb2,
str1,
str2,
jsr1,
jsr2,
s_shf
/* (see Appendix E) */
} state, next_state;
always_comb
begin : state_actions
/* Default output assignments */
/* Default assignments */
load_pc = 1'b0;
load_ir = 1'b0;
load_regfile = 1'b0;
load_mar = 1'b0;
load_mdr = 1'b0;
load_cc = 1'b0;
pcmux_sel = 2'b00;
storemux_sel = 1'b0;
alumux_sel = 2'b00;
regfilemux_sel = 3'b000;
marmux_sel = 1'b0;
mdrmux_sel = 1'b0;
aluop = alu_add;
mem_read = 1'b0;
mem_write = 1'b0;
mem_byte_enable = 2'b11;
/*(see Appendix E) */
case(state)
fetch1: begin
/* MAR <= PC */
marmux_sel = 1;
load_mar = 1;
/* PC <= PC + 2 */
pcmux_sel = 0;
load_pc = 1;
end
fetch2: begin
/* Read memory */
mem_read = 1;
mdrmux_sel = 1;
load_mdr = 1;
end
fetch3: begin
/* Load IR */
load_ir = 1;
end
decode: /* Do nothing */;
s_add: begin
/* DR <= SRA + SRB */
aluop = alu_add;
load_regfile = 1;
regfilemux_sel = 0;
load_cc = 1;
if (bit5 == 1)
alumux_sel = 2'b10;
end
s_not: begin
/* DR <= NOT(SRA) */
aluop = alu_not;
load_regfile = 1;
load_cc = 1;
end
s_and: begin
/* DR <= SRA & SRB */
aluop = alu_and;
load_regfile = 1;
load_cc = 1;
if (bit5 == 1)
alumux_sel = 2'b10;
end
s_jmp: begin
/* PC <= BASE R (SR2) */
pcmux_sel = 2'b10;
load_pc = 1;
end
s_jsr: begin
/* R7 <= PC */
storemux_sel = 1;
load_regfile = 1;
regfilemux_sel = 3'b011;
end
jsr1: begin
/* PC <= BASE R (SR2) */
pcmux_sel = 2'b10;
load_pc = 1;
end
jsr2: begin
/* PC = PC + offset11 */
regfilemux_sel = 3'b100;
pcmux_sel = 2'b01;
load_pc = 1;
end
s_lea: begin
/* DR <= PC + SEXT(PCoffset9)<<1 */
regfilemux_sel = 3'b010;
load_regfile = 1;
load_cc =1;
end
s_trap: begin
/* MAR <= ZEXT(trapvect8)<<1 */
addr1mux_sel = 0;
marmux_sel = 2'b10;
load_mar = 1;
end
trap1: begin
/* MDR <= M(MAR) */
mdrmux_sel = 1;
load_mdr = 1;
mem_read = 1;
/* R7 <= PC */
storemux_sel = 1;
load_regfile = 1;
regfilemux_sel = 3'b011;
end
trap2: begin
/* PC <= MDR */
pcmux_sel = 2'b11;
load_pc = 1;
end
br: /* Do nothing */ ;
br_taken: begin
/* PC<= PC + SEXT(IR[8:0] << 1) */
pcmux_sel = 1;
load_pc = 1;
end
calc_addr: begin
/* MAR <= SRA + SEXT(IR[5:0] << 1) */
alumux_sel = 1;
aluop = alu_add;
load_mar = 1;
end
ldr1: begin
/* MDR <= M[MAR] */
mdrmux_sel = 1;
load_mdr = 1;
mem_read = 1;
end
ldr2: begin
/* DR <= MDR */
regfilemux_sel = 1;
load_regfile = 1;
load_cc = 1;
end
s_ldb: begin
/* MAR <= SR1 + sext(offset6)*/
marmux_sel = 2'b11;
addr1mux_sel = 1;
load_mar = 1;
end
ldb1: begin
/* MDR <= M[MAR] */
mdrmux_sel = 1;
load_mdr = 1;
mem_read = 1;
end
ldb2: begin
/* DR <= MDR */
regfilemux_sel = 3'b010;
if(mem_byte == 0)
hilomux_sel = 2'b00;
else
hilomux_sel = 2'b01;
load_regfile = 1;
load_cc = 1;
end
s_ldi: begin
/* MDR <= M[MAR] */
mdrmux_sel = 1;
load_mdr = 1;
mem_read = 1;
end
ldi1: begin
/* MAR <= MDR */
marmux_sel = 2'b10;
load_mar = 1;
end
ldi2: begin
/* MDR <= M[MAR] */
mdrmux_sel = 1;
load_mdr = 1;
mem_read = 1;
end
ldi3: begin
/* DR <= MDR */
regfilemux_sel = 1;
load_regfile = 1;
load_cc = 1;
end
s_stb: begin
/* MAR <= SR1 + SEXT(offset6) */
addr1mux_sel = 1;
marmux_sel = 2'b11;
load_mar = 1;
end
stb1: begin
storemux_sel = 1'b1;
aluop = alu_act;
mdrmux_sel = 1'b0;
load_mdr = 1;
end
stb2: begin
/* M[MAR] <= MDR */
if(mem_byte == 0)
mem_byte_enable = 2'b01;
else
mem_byte_enable = 2'b10;
mem_write = 1;
end
s_sti: begin
/* MDR <= M[BaseR + sext(offset6)] */
mdrmux_sel = 1;
load_mdr = 1;
mem_read = 1;
end
sti1: begin
/* MAR <= MDR */
marmux_sel = 2'b10;
load_mar = 1;
end
sti2: begin
storemux_sel = 1;
aluop = alu_pass;
mdrmux_sel = 0;
load_mdr = 1;
mem_read = 1;
end
sti3: begin
mem_write = 1;
end
str1: begin
/* MDR <= SR */
storemux_sel = 1;
aluop = alu_pass;
load_mdr = 1;
end
str2: begin
/* M[MAR] <= MDR */
mem_write = 1;
end
default: /* Do nothing */;
endcase
/* Actions for each state */
end
always_comb
begin : next_state_logic
/* Next state information and conditions (if any)
* for transitioning between states */
next_state = state;
case(state)
fetch1: begin
next_state = fetch2;
end
fetch2: begin
if(mem_resp == 0)
next_state = fetch2;
else
next_state = fetch3;
end
fetch3: begin
next_state = decode;
end
decode: begin
case(opcode)
op_add: begin
next_state = s_add;
end
op_and: begin
next_state = s_and;
end
op_br: begin
next_state = br;
end
op_not: begin
next_state = s_not;
end
op_ldr: begin
next_state = calc_addr;
end
op_ldi :begin
next_state = s_ldi;
end
op_ldb : begin
next_state = s_ldb;
end
op_stb: begin
next_state = s_stb;
end
op_sti: begin
next_state = s_sti;
end
op_str: begin
next_state = calc_addr;
end
op_lea: begin
next_state = s_lea;
end
op_trap: begin
next_state = s_trap;
end
op_jmp: begin
next_state = s_jmp;
end
op_jsr: begin
next_state = s_jsr;
end
op_shf: begin
next_state = s_shf;
end
default: ;/* Do nothing */
endcase
end
s_add: begin
next_state = fetch1;
end
s_and: begin
next_state = fetch1;
end
s_not: begin
next_state = fetch1;
end
s_trap: begin
next_state = trap1;
end
trap1: begin
if(mem_resp == 0)
next_state = trap1;
else
next_state = trap2;
end
trap2: begin
next_state = fetch1;
end
calc_addr: begin
if(opcode == op_ldr)
next_state = ldr1;
else
next_state = str1;
end
ldr1: begin
if(mem_resp == 0)
next_state = ldr1;
else
next_state = ldr2;
end
ldr2: begin
next_state = fetch1;
end
s_ldb:begin
next_state = ldb1;
end
ldb1:begin
if(mem_resp == 0)
next_state = ldb1;
else
next_state = ldb2;
end
ldb2:begin
next_state = fetch1;
end
s_ldi: begin
if(mem_resp == 0)
next_state = s_ldi;
else
next_state = ldi1;
end
ldi1:begin
next_state = ldi2;
end
ldi2:begin
if(mem_resp == 0)
next_state = ldi2;
else
next_state = ldi3;
end
ldi3:begin
next_state = fetch1;
end
s_shf:begin
/* shift */
load_regfile = 1;
load_cc = 1;
alumux_sel = 2'b11;
regfilemux_sel = 3'b000;
if(bit5== 1'b0)
aluop = alu_srl;
else if (bit4 == 1'b0)
aluop = alu_sll;
else
aluop = alu_sra;
end
s_stb: begin
next_state = stb1;
end
stb1: begin
next_state = stb2;
end
stb2:begin
if(mem_resp == 0)
next_state = stb2;
else
next_state = fetch1;
end
s_sti: begin
if(mem_resp == 0)
next_state = s_sti;
else
next_state = sti1;
end
sti1:begin
next_state = sti2;
end
sti2:begin
next_state = sti3;
end
sti3:begin
if(mem_resp == 0)
next_state = sti3;
else
next_state = fetch1;
end
str1: begin
next_state = str2;
end
str2: begin
if(mem_resp == 0)
next_state = str2;
else
next_state = fetch1;
end
br: begin
if(br_en == 1)
next_state = br_taken;
else
next_state = fetch1;
end
br_taken: begin
next_state = fetch1;
end
s_jmp: begin
next_state = fetch1;
end
s_jsr: begin
if (bit11 == 0)
next_state = jsr1;
else
next_state = jsr2;
end
jsr1: begin
next_state = fetch1;
end
jsr2: begin
next_state = fetch1;
end
s_lea: begin
next_state = fetch1;
end
s_shf: begin
next_state = fetch1;
end
/*default: begin
end*/
endcase
end
always_ff @(posedge clk)
begin: next_state_assignment
/* Assignment of next state on clock edge */
state <= next_state;
end
endmodule : control
... так в чем была проблема? – duskwuff